The present invention relates to digital time delay circuits of the type in which data is read into memory in a circulating fashion and read from the memory in a similar fashion, except that the read addresses are offset from the write addresses so as to produce a selected time delay.
In a prior art approach to the type of time delay circuit described, a single memory device with plural storage locations is used. Data is written into the memory and read from it on alternate cycles. A limitation of such an approach is that the memory can accept data at only half the maximum operating rate of the memory device.
A second prior art approach is shown in FIG. 1. There, two eight bit memory devices R and S are illustrated. It should be borne in mind that in such delay circuits, the storage locations employed typically number in the thousands; the small memory devices shown herein are for purposes of illustration. In FIG. 1, numbers 0 through 7 are shown beside small blocks representing bit storage locations. The numbers represent the addresses of the locations. Both read and write addresses are generated by a counter which counts repeatedly from 0 to 7. The address thus generated is alternately applied to memory R and memory S. The results of applying the write address in this fashion are shown for a sequence of bits b0-b7. Bit b0 is stored in location 0 of memory R, while the next bit b1 is stored in location 1 of memory S, etc. After the storage of bit b7 in location 7 of memory S, then the next bit is stored in location 0 of memory R.
To achieve a delay of, say, five bit intervals, the read address could begin accessing location 0 of memory R, while the write address is entering a bit in location 5 of memory S. The advantage of the operation of FIG. 1 is that memory S can be written into at the same time memory R is being read from and vice versa. This enables the memories to process data at the maximum operating rate of the memory devices.
The disadvantage of the operation of FIG. 1 is that half the memory locations in the memory devices are not used. Thus, for a given delay, there will be required memory devices having twice the number of storage locations as the number of bit intervals required for the delay.